XMC16DAC8: High Speed Acoustic AWG and Signal Generator XMC (Switched Mezzanine Card), Rugged interface VITA 42 (XMC 1.0)
  • Eight channel signal generators in XMC on RF MMCX (Micro-Miniature Coaxial).
  • 16-bit I/Q DACs. Sample rate programmable up to 200 MSPS.
  • On board interpolation filters and direct digital synthesizer in FPGA logic.
  • 4 lane Gen 2 PCI Express interface with DMA engine, 256MB waveform memory.

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High Performance Fundamentals

The XMC16DAC8 is an eight-channel high frequency (HF) signal generator in half-length half-height PCIe form factor. The card provides eight fully differential analog output channels, which are sourced from synchronous 16-bit DACs which may be clocked at up to 200MHz. The analog output is fixed at 20Vp-p differential for full scale digital inputs, and includes two pole reconstruction filtering. All other processing is performed using the on-board FPGA resources. The XMC16DAC8 includes a high precision frequency synthesizer which allows the user to generate a sample clock of virtually any frequency. It can also accept an external clock for frequency coherent synchronization to peripheral equipment. When using the XMC16DAC8, data acquisition may be performed in either loop, pulse, or continuous mode. In pulse mode a specific number of samples are converted following a trigger event. In loop mode a specified buffer (up to 16M samples) in local memory is repetitively fed to the converters. Continuous mode allows the user to feed data from the host system over the PCIe interface. The amount data acquired is virtually unlimited, but the data rate will be limited by the bandwidth of the PCIe connection. Conversion may be initiated and terminated by software commands, or by the external trigger/gate input.

On board processing

The XMC16DAC8 includes on board processing resources to support operation as a multi-channel AWG or signal generator. The card can accept data streamed from a host processor in real time, it can operate on previously buffered data, or it can generate it’s own waveform data based on a direct digital synthesis core. or the internal clock may be phase locked to a lower frequency, such as a 10MHz system reference clock.

Architecture and Functionality

  • Sigma-delta data acquisition card in XMC Form Factor.
  • 256 MB DDR3 DRAM memory.
  • Xilinx Artix 7 FPGA: Artix 7
  • QSPI Flash memory for FPGA configuration, calibration data, etc.
  • Supports continuous, pulse, and loop modes of operation.
  • x4 PCI Express (Gen 2). Includes DMA engine with 64 bit addressing capability.
  • Total power dissipation approximately 9W. (estimated)

    • Analog Outputs

  • 8 analog output channels. Can be used independently, or as 4 complex (I/Q) channels.
  • 50 Ohm output impedance. Two pole low pass anti-alias filter. Fc 10 MHz
  • Fixed 20Vp-p differential output at full scale digital input. Contact factory if a different value is required.
  • 16-bit DAC I/Q DACs. Sample rate programmable up to 200 MSPS.
  • Noise spectral density < 150dBc/Hz NSD (10MHz out @ 200MSPS)
  • SFDR >79dB (10MHz output signal @ 100MSPS input data rate)
  • Analog IO uses MMXC connectors. Front panel or rear IO (VITA67) options available